
* May 16 2009

Command-line option "-mr10k-cache-barrier[=1|store|2|load-store|none]"

* Mar  5 2006

1) Command-line option "-mr10k-cache-barrier[=1|2]", where
   "=1" or missing option-argument enables cache-barriers before stores only,
   "=2" enables cache-barriers before stores and loads.
   "-mip28-cache-barrier" is no longer recommended.

2) Added patch for gcc 4.2 (mips.c, mips.opt).
3) Using "for_each_rtx()" reduces source-size.
4) Minor cleanup.

* Feb 19 2006

The "new" version now only changes mips.[ch].

* Dec 31 2005

1) Get rid of some unnecessary cache-barriers.

2) Added a "new" version, which works with an additional compiler-pass
   instead of hooks in final[_scan_insn]().
   It's yet implemented for 4.0.1 only, but this patch should easily be 
   applied "manually" to 3.x as well as to future gcc-versions.
   As far as i could check, it generates (essentialy) the same code as
   the "old-style" version.  If anyone experiences differences though,
   please let me know.


* Sep 25 2005

1) Added Version for gcc 4.0.1
2) Moved most of the IP28-specific code from final.c to config/mips/mips.c
   for gcc 3.4.2 and 4.0.1

* Apr  6 2005

1) Refined scan for memory operands in "(set(..." instructions.
2) Protect load instructions too by cache barriers.
   (While speculative loads do not cause harmful write-backs, they too
   can initiate accesses to invalid memory bus addresses)
3) Avoid cache barriers before loads/stores from/to constant addresses
   ("symbol_ref", ...)
4) Treat inline assembly as containing potentially harmful loads/stores.
   (To keep header files and the like (mostly) free from cache barriers)

Now all potentially harmful load/store instructions should be caught,
and much fewer unnecessary cache barriers will be generated.


* Nov 18 2004

With respect to cache barriers, it's advisable to handle calls like
conditional branches.

* Sep 18 2004

Added patches for gcc 3.4.2.
Some cleanup (`config/mips/mips.[ch], final.c' instead of `toplev.c, final.c'
...).
Switch on cache-barrier generation with `-mip28-cache-barrier' now.
Additional kernel patch inserts this option into Makefiles (requires
that IP28 kernel-patches are already appplied).

* Sep  8 2004

Improved by taking `set .reorder/.noreorder' into account.

* Sep  1 2004

Here you find a little patch to make gcc (2.95.4) generate appropriate cache
barriers to 0(sp) at the start of each basic block, which contains critical
store instructions.
If you wonder, what this is all about, read:

- MIPS R10000 Microprocessor User's Manual, Version 2.0,
  "Side Effects of Speculative Execution"

- http://mail-index.netbsd.org/port-sgimips/2000/06/29/0006.html

- The README file accompaning the kernel patches at this site.

This patch is not a especially proper modification to gcc (local machine-
dependent definitions in final.c, ... instead of using machine-definition-,
header-files, etc.), but it does what is needed and affects two files only:

- final.c, where all modifications to code generation are done.

- toplev.c, to turn generation of these cache-barriers on/off with the
  `-fip28-cache-barrier/-fno-ip28-cache-barrier' option.
  Default is `off' (`-fno-ip28-cache-barrier').

Reports on success (or bugs :-() are welcome.

